View UPD720122_183342.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET MOS Integrated Circuit
PD720122
USB2.0 Generic Device Controller
The PD720122 is USB2.0 Generic Device Controller, which combines the NEC Electronics USB2.0 PHY and Endpoint Controller. The Controller has certified by USB Implementers Forum. End-point Controller has banked two Bulk Endpoint and one Interrupt End-point, and selectable three general CPU bus-types, suitable for designing various USB device. The controller has the external local bus, that enables to perform high speed data transferring when CPU is accessing to the controller. These IP Blocks in the controller are based completely on an NEC Electronics ASIC core, so PD720122 is suitable to design for the prototype system that are intended to design ASIC in the future.
Detailed function descriptions are provided in the following user's manual. Be sure to read the manual before designing.
PD720122 User's Manual: S15829E
FEATURES
* Complaint with USB2.0 specification (Maximum data transferring rate: 480 Mbps) * USB2.0 certified (TestID=40000822) * High(480Mbps) / Full(12Mbps)- Speed support and switch automatically * Easy to design NEC Electronics ASIC * Generic USB2.0 Device Controller * Two Bulk End-points and One Interrupt End-point * Performed Data Local Bus independent from CPU bus. (Maximum Data Transferring rate: 21 MBps with DMA mode ) * Selectable three CPU Bus Interface
ORDERING INFORMATION
Part Number Package 100-pin plastic TQFP (Fine pitch) (14 x 14) 109-pin plastic FBGA (11 x 11)
PD720122GC-9EU PD720122F1-DN2
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S16685EJ2V0DS00 (2nd edition) Date Published June 2003 NS CP (K) Printed in Japan
The mark
shows major revised points.
2003
PD720122
BLOCK DIAGRAM
EPC2 Core Protocol Controller EP0 Control IN 64 Byte EP0 Control OUT 64 Byte Local BUS EP1 BulkOUT 512 Byte x2 USB BUS
BIU Core CPU BUS
PHY Core
EP2 BulkIN 512 Byte x2 EP3 Interrupt IN 8 Byte
PHY Core EPC2 Core BIU Core
: USB2.0 transceiver with serial interface engine : Endpoint controller : Bus Interface Unit
2
Data Sheet S16685EJ2V0DS
PD720122
PIN CONFIGURATION
* 100-pin plastic TQFP (Fine pitch) (14 x 14)
PD720122GC-9EU
Top View
Remark The function of the pin is shown with Function 1/Function 2/Function 3 from the left.
Data Sheet S16685EJ2V0DS
3
PD720122
PD720122GC-9EU
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name Function1 VDD RESETB GND XIN_CLK XOUT GND CSB INTB_ALL A1 A2 A3 A4 A5 A6 A7 GND D0 D1 D2 D3 D4 D5 D6 D7 VDD Pin Name Function2 VDD RESETB GND XIN_CLK XOUT GND CSB ALE INTB_ALL Reserved Reserved Reserved Reserved Reserved Reserved GND AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VDD Pin Name Function3 VDD RESETB GND XIN_CLK XOUT GND CSB ALE INTB_ALL Reserved Reserved Reserved Reserved Reserved Reserved GND D0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VDD Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name Function1 GND D8 D9 D10 D11 D12 D13 D14 D15 VDD GND WRB RDB INT0B INT1B INT2B ACTIVE SCAN1 SCAN0 M2 EP1_DRQB EP1_DACKB EP1_RDB EP1_TCB GND Pin Name Function2 GND Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved VDD GND WRB RDB INT0B INT1B INT2B ACTIVE SCAN1 SCAN0 M2 EP1_DRQB EP1_DACKB EP1_RDB EP1_TCB GND
(1/2)
Pin Name Function3 GND D8 D9 D10 D11 D12 D13 D14 D15 VDD GND WRB RDB INT0B INT1B INT2B ACTIVE SCAN1 SCAN0 M2 EP1_DRQB EP1_DACKB Reserved EP1_TCB GND
4
Data Sheet S16685EJ2V0DS
PD720122
PD720122GC-9EU
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name Fucntion1 VDD FM21 EP2_DRQB EP2_DACKB EP2_WRB EP2_TCB LD0 LD1 LD2 LD3 GND LD4 LD5 LD6 LD7 LD8 LD9 GND LD10 LD11 LD12 LD13 LD14 LD15 VDD Pin Name Function2 VDD FM21 EP2_DRQB EP2_DACKB EP2_WRB EP2_TCB LD0 LD1 LD2 LD3 GND LD4 LD5 LD6 LD7 LD8 LD9 GND LD10 LD11 LD12 LD13 LD14 LD15 VDD Pin Name Function3 VDD FM21 EP2_DRQB EP2_DACKB Reserved EP2_TCB Reserved Reserved Reserved Reserved GND Reserved Reserved Reserved Reserved Reserved Reserved GND Reserved Reserved Reserved Reserved Reserved Reserved VDD Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name Fucntion1 GND BUNRI RREF AVSS(R) AVDD AVSS RPU VSS RSDP DP VDD DM RSDM VSS NC PVSS NC PVDD VSS VDD VSS M1 M0 VBUS GND Pin Name Function2 GND BUNRI RREF AVSS(R) AVDD AVSS RPU VSS RSDP DP VDD DM RSDM VSS NC PVSS NC PVDD VSS VDD VSS M1 M0 VBUS GND
(2/2)
Pin Name Function3 GND BUNRI RREF AVSS(R) AVDD AVSS RPU VSS RSDP DP VDD DM RSDM VSS NC PVSS NC PVDD VSS VDD VSS M1 M0 VBUS GND
Remark AVSS (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 k.
Data Sheet S16685EJ2V0DS
5
PD720122
* 109-pin plastic FBGA (11 x 11)
PD720122F1-DN2
Bottom View
Remarks The pin name is showing it with Function1. As for the pin name of Function2 and Function3, please refer to the table of the next page.
6
Data Sheet S16685EJ2V0DS
PD720122
PD720122F1-DN2
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name Function1 NC D8 D10 D12 D15 GND INT1B ACTIVE M2 EP1_DACKB EP1_TCB NC FM21 EP2_DACKB EP2_TCB LD2 GND LD7 LD9 LD11 LD13 LD15 NC BUNRI AVSS(R) Pin Name Function2 NC Reserved Reserved Reserved Reserved GND INT1B ACTIVE M2 EP1_DACKB EP1_TCB NC FM21 EP2_DACKB EP2_TCB LD2 GND LD7 LD9 LD11 LD13 LD15 NC BUNRI AVSS(R) Pin Name Function3 NC D8 D10 D12 D15 GND INT1B ACTIVE M2 EP1_DACKB EP1_TCB NC FM21 EP2_DACKB EP2_TCB Reserved GND Reserved Reserved Reserved Reserved Reserved NC BUNRI AVSS(R) Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name Function1 AVSS RSDP VDD NC NC VDD M1 VBUS NC RESETB XIN_CLK GND A1 A3 A7 D0 D3 D5 D7 NC D9 D11 D14 RDB INT2B Pin Name Function2 AVSS RSDP VDD NC NC VDD M1 VBUS NC RESETB XIN_CLK GND INTB_ALL Reserved Reserved AD0 AD3 AD5 AD7 NC Reserved Reserved Reserved RDB INT2B
(1/2)
Pin Name Function3 AVSS RSDP VDD NC NC VDD M1 VBUS NC RESETB XIN_CLK GND INTB_ALL Reserved Reserved D0 AD3 AD5 AD7 NC D9 D11 D14 RDB INT2B
Remark AVSS (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 k.
Data Sheet S16685EJ2V0DS
7
PD720122
PD720122F1-DN2
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name Function1 SCAN0 EP1_DRQB EP1_RDB NC EP2_DRQB EP2_WRB LD1 LD5 LD8 LD10 LD12 LD14 NC RREF AVDD GND RSDM PVSS GND GND M0 NC GND XOUT INTB_ALL A5 GND D2 D4 D6 Pin Name Function2 SCAN0 EP1_DRQB EP1_RDB NC EP2_DRQB EP2_WRB LD1 LD5 LD8 LD10 LD12 LD14 NC RREF AVDD GND RSDM PVSS GND GND M0 NC GND XOUT ALE Reserved GND AD2 AD4 AD6 Pin Name Function3 SCAN0 EP1_DRQB Reserved NC EP2_DRQB Reserved Reserved Reserved Reserved Reserved Reserved Reserved NC RREF AVDD GND RSDM PVSS GND GND M0 NC GND XOUT ALE Reserved GND AD2 AD4 AD6 Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Pin Name Function1 GND D13 VDD INT0B WRB SCAN1 VDD GND LD0 LD3 LD6 LD4 GND VDD GND RPU DP GND DM PVDD VDD GND CSB A2 A6 A4 D1 VDD GND Pin Name Function2 GND Reserved VDD INT0B WRB SCAN1 VDD GND LD0 LD3 LD6 LD4 GND VDD GND RPU DP GND DM PVDD VDD GND CSB Reserved Reserved Reserved AD1 VDD GND -
(2/2)
Pin Name Function3 GND D13 VDD INT0B WRB SCAN1 VDD GND Reserved Reserved Reserved Reserved GND VDD GND RPU DP GND DM PVDD VDD GND CSB Reserved Reserved Reserved AD1 VDD GND -
8
Data Sheet S16685EJ2V0DS
PD720122
1. PIN INFORMATION
(1/2)
Pin Name I/O Buffer Type Active Level RESETB XIN_CLK XOUT CSB INTB_ALL ALE A(7:1) D(15:0) AD(7:0) D0 AD(7:1) D(15:8) WRB RDB INT0B INT1B INT2B ACTIVE SCAN(1:0) M2 EP1_DRQB EP1_DACKB EP1_RDB EP1_TCB FM21 EP2_DRQB EP2_DACKB EP2_WRB EP2_TCB LD(15:0) BUNRI RREF RPU RSDP DP DM I I O I O I I I/O I/O I/O I/O I/O I I O O O I I O O I I I I O I I I I/O I A A O I/O I/O 5 V tolerant Input Schmitt 3.3 V Input 3.3 V Output 5 V tolerant Input 5 V tolerant Output 5 V tolerant Input 5 V tolerant Input 5 V tolerant I/O 5 V tolerant I/O 5 V tolerant I/O 5 V tolerant I/O 5 V tolerant I/O 5 V tolerant Input 5 V tolerant Input 5 V tolerant Output 5 V tolerant Output 5 V tolerant Output 5 V tolerant Input 3.3 V Input 50 k Pull Down 5 V tolerant Output 5 V tolerant Output 5 V tolerant Input 5 V tolerant Input 5 V tolerant Input 3.3 V Input 5 V tolerant Output 5 V tolerant Input 5 V tolerant Input 5 V tolerant Input 5 V tolerant I/O 5V torelant Input Analog USB pull-up control USB full speed D+ O USB high speed D+ I/O USB high speed D- I/O Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low High Low Asynchronous reset signaling System clock input or oscillator In Oscillator out Chip select signal Interrupt request signal Address strobe signal (Function2/3) Address input (Function1) Data bus (I/O) (Function1) Address/data multiplexed bus (I/O) (Function2) Data bus (I/O) (Function3) Address/data multiplexed bus (I/O) (Function3) Data bus (I/O) (Function3) Write command input Read command input Interrupt request (INT Status 0) Interrupt request (INT Status 1) Interrupt request (INT Status 2) DMA-related pins active level select(Function2/3) Chip test pin. Status output pin DMA transfer request output pin of EP1 DMA transfer enable input pin of EP1 DMA Read command input pin of EP1 DMA terminal count input pin of EP1 NEC Electronics test pin DMA transfer request output pin of EP2 DMA transfer enable input pin of EP2 DMA Write command input pin of EP2 DMA terminal count input pin of EP2 Data bus (I/O) pin for external local bus NEC Electronics test pin Reference resistor USB's 1.5 k pull-up resistor control USB's full speed D+ signal USB's high speed D+ signal USB's high speed D- signal Function
Data Sheet S16685EJ2V0DS
9
PD720122
(2/2)
Pin Name RSDM M(1:0) VBUS AVDD, PVDD VDD AVSS, PVSS VSS, GND NC Reserved I/O O I I Buffer Type USB full speed D- O 5 V tolerant Input 5 V tolerant Input
Note
Active Level
Function USB's full speed D- signal Function mode setting VBUS monitoring 3.3 VDD for Analog circuit 3.3 VDD VSS for Analog circuit VSS Not connect Not used
Note
VBUS pin may be used to monitor for VBUS line even if VDD, AVDD, and PVDD are shut off. System must ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is not exceeded.
Remark
"5 V tolerant" means that the buffer is 3.3 V buffer with 5 V tolerant circuit.
The operation mode of the BIU can be set by external pins, as shown below. Fix external pins (M1 and M0) when using them.
Pin M1 0 0 M0 0 1 16-bit mode (Function 1) 8-bit mode (Function 2) A 16-bit CPU bus and an external local bus dedicated to data transfer for bulk IN/OUT can be used in this mode. The internal register length is 16 bits. Multiplexed bus mode of 8-bit address bus and 8-bit data bus. The register length is 8 bits only in this mode (registers can only be accessed in byte units). Therefore, the address space in this mode differs from that in the other modes. The active levels of some external local bus control pins can be changed by the Active pin. Multiplexed bus mode of 8-bit address bus and 16-bit data bus. The internal register length is 16 bits. The active levels of some external local bus control pins can be changed by the Active pin. Setting prohibited BIU Operation Mode Outline
1
0
16-bit mix mode (Function 3) Setting prohibited (Function 4)
1
1
10
Data Sheet S16685EJ2V0DS
PD720122
2. ELECTRICAL SPECIFICATIONS
2.1
Buffer List
* 3.3 V oscillator interface XIN,XOUT * 3.3 V input buffer FM21,SCAN(1:0) * 5V torelant input buffer RESETB,CSB,A(7:0),WRB,RDB,ACTIVE,EP1_DACKB,EP1_RDB,EP1_TCB,EP2_DACKB,EP2_WRB, EP2_TCB,BUNRI,M0,M1,VBUS,ALE * 5V torelant output buffer INTB_ALL,INT0B,INT1B,INT2B,M2,EP1_DRQB,EP2_DRQB * 5V torelant I/O buffer D(15:0),LD(15:0),AD(7:0),D0,AD(7:1),D(15:8) * USB interface DP,DM,RSDP,RSDM,RREF,RPU
2.2
Terminology
Terms Used in Absolute Maximum Ratings
Parameter Power supply voltage Symbol VDD Meaning Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Indicates absolute tolerance value for DC current to prevent damage or reduced reliability when a current flows out of or into an output pin. Indicates the ambient temperature range for normal logic operations. Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device.
Input voltage
VI
Output voltage
VO
Output current
IO
Operating temperature Storage temperature
TA Tstg
Data Sheet S16685EJ2V0DS
11
PD720122
Terms Used in Recommended Operating Range
Parameter Power supply voltage High-level input voltage Symbol VDD VIH Meaning Indicates the voltage range for normal logic operations occur when VSS = 0 V. Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the "Min." value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the "Max." value is applied, the input voltage is guaranteed as low level voltage. Hysteresys voltage VH Indicates the differential between the positive trigger voltage and the negative trigger voltage. Indicates allowable input rise time to input pins. Input rise time is transition time from 0.1 x VDD to 0.9 x VDD. Indicates allowable input fall time to input pins. Input fall time is transition time from 0.9 x VDD to 0.1 x VDD.
Input rise time
tri
Input fall time
tfi
Terms Used in DC Characteristics
Parameter Off-state output leakage current Output short circuit current Symbol IOZ Meaning Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Indicates the current that flows when the output pin is shorted (to GND pins) when output is at high-level. Indicates the current that flows when the input voltage is supplied to the input pin. Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. Indicates the current that flows from the output pins when the rated high-level output voltage is being applied.
IOS
Input leakage current Low-level output current
II IOL
High-level output current
IOH
12
Data Sheet S16685EJ2V0DS
PD720122
2.3 Absolute Maximum Ratings
Parameter Voltage I/O voltage Note 1 Note 2 Output current Note 3 Operating ambient temperature Storage temperature
Symbol VDD VI/VO
Conditions
Ratings -0.5 to +4.6
Unit V
VI/VO < VDD+3.0 V VI/VO < VDD+0.3 V IO IOL = 6 mA TA Tstg
-0.5 to +6.6 -0.5 to +4.6
V V
6 0 to +70 -65 to +150
mA C C
Notes 1. 2. 3.
5 V torelant input buffer, output buffer, I/O buffer 3.3 V input buffer,3.3 V oscillator interface 5 V torelant output buffer, I/O buffer(OUT)
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
2.4
Recommended Operating Range
Parameter Power supply voltage Negative trigger voltage Positive trigger voltage Hysteresis voltage Input voltage, low Input voltage, high
Symbol VDD VN VP VH VIL VIH 3.3 V Power
Conditions
Min. 3.0 0.6 1.2 0.3 0
Typ. 3.3
Max. 3.6 1.8 2.4 1.5 0.8 VDD 5.5 200
Unit V V V V V V V ns
3.3 V input buffer 5V torelant input buffer, I/O buffer
2.0 2.0 0
Rise/fall time
tr/tf
Data Sheet S16685EJ2V0DS
13
PD720122
2.5 DC Characteristics
The DC characteristics are classified into those of the USB interface and those of the BIU block.
2.5.1
DC characteristics of USB interface
Parameter Serial resistor between DP (DM) and RSDP (RSDM) Driver output resistance (also serves as high-speed termination) Bus pull-up resistor on upstream facing port Termination voltage for upstream facing port pull-up (full-speed) Input levels for full-speed: High-level input voltage (driven) High-level input voltage (floating) Low-level input voltage Differential input sensitivity Differential common mode range Output levels for full-speed: High-level output voltage Low-level output voltage SE1 Output signal crossover voltage Input levels for high-speed: High-speed squelch detection threshold (differential signal amplitude) High-speed disconnect detection threshold (differential signal amplitude) High-speed data signaling common mode voltage range (guideline for receiver) High-speed differential input signaling level Output levels for high-speed: High-speed idle level High-speed data signaling high High-speed data signaling low Chirp J level (different voltage) Chirp K level (different voltage)
Symbol RS ZHSDRV RPU VTERM
Conditions
Min. 35.64
Max. 36.36 49.5 1.575 3.6
Unit V
Includes RS resistor
40.5 1.425 3.0
VIH VIHZ VIL VDI VCM (D+) - (D-) Includes VDI range
2.0 2.7 3.6 0.8 0.2 0.8 2.5
V
V V V
VOH VOL VOSE1 VCRS
RL of 14.25 k to VSS RL of 1.425 k to 3.6 V
2.8 0.0 0.8 1.3
3.6 0.3
V V V
2.0
V
VHSSQ VHSDSC VHSCM See Figure 2-4
100 525 -50
150 625 500
mV mV mV
VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK
-10.0 360 -10.0 700 -900
10 440 10 1100 -500
mV mV mV mV mV
14
Data Sheet S16685EJ2V0DS
PD720122
Figure 2-1. Differential Input Sensitivity Range for Low-/Full-Speed
Differential input voltage range Differential output crossover voltage range
-1.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
4.6
Input voltage range (volts)
Figure 2-2. Full-Speed Buffer Voh/Ioh Characteristics for High-Speed Capable Transceiver
VDD-3.3
VDD-2.8 VDD-2.3
VDD-1.8 VDD-1.3 VDD-0.8
VDD-0.3 VDD 0
-20
Iout (mA)
-40 Min -60 Max -80 Vout (V)
Data Sheet S16685EJ2V0DS
15
PD720122
Figure 2-3. Full-Speed Buffer Vol/Iol Characteristics for High-Speed Capable Transceiver
80 Max 60
Iout (mA)
Min 40
20
0 0 0.5 1 1.5 Vout (V) 2 2.5 3
Figure 2-4. Receiver Sensitivity for Transceiver at D+/D- -
Level 1
+400 mV differential
Point 3
Point 4
Point 1
Point 2
0V differential
Point 5
Point 6
Level 2
-400 mV differential
0%
Unit interval
100%
16
Data Sheet S16685EJ2V0DS
PD720122
Figure 2-5. Receiver Measurement Fixtures
Test supply voltage 15.8 USB connector nearest device Vbus D+ DGnd 50- Coax 50- Coax + To 50- input of a high-speed differential oscilloscope, or 50- outputs of a high-speed differential data generator -
15.8
143
143
Data Sheet S16685EJ2V0DS
17
PD720122
2.5.2 DC characteristics of BIU
Parameter Off-state output current Output short current Input leakage current Output current, low Output current, high Output voltage, low Output voltage, high
Symbol IOZ IOS II IOL IOH VOL VOH
Conditions VO = VDD or GND
Min.
Typ.
Max. 10 -250
Unit
A
mA
VI = VDD or GND VOL = 0.4 V
Note
10-5 6 -2 0.1 VDD-0.2
A
mA mA V V
VOH = 2.4 V IOL = 0 mA IOH = 0 mA
Note
5V-Tolerant Output
18
Data Sheet S16685EJ2V0DS
PD720122
2.5.3 Pin capacitance
Parameter Input capacitance Output/bidirectional capacitance
Symbol CIN COUT
Conditions
Min. 4.5 8.5
Typ.
Max. 6.5 11
Unit pF pF
Remark These are just estimated values.
2.5.4
Power consumption
Parameter Power consumption
Symbol PH HS mode
Conditions VDD AVDD
Min.
Typ. 195 12 120 12 1.5 0.1 370 0.1
Max. 273 17 168 17 2.2 0.2 520 0.2
Unit mA mA mA mA mA
PF
FS mode
VDD AVDD
PS1
Suspend mode 1
Note 1
VDD AVDD
A A A
PS2
Suspend mode 2
Note 2
VDD AVDD
Notes 1. 2.
SND PHY Reg. SPND bit = 1 SND PHY Reg. SPND bit = 1 GPR Reg. CONNECTB bit = 0 GPR Reg. PUE bit = 0 BIU Control 0 Reg. OSC_DISCONB bit = 1
Data Sheet S16685EJ2V0DS
19
PD720122
2.6 AC Characteristics (TA = 0 to +70C, VDD = 3.3 V 10%)
The AC characteristics are classified into those of the USB interface block and those of the BIU.
2.6.1
Overall AC characteristics and those of BIU
(1) Clock
Parameter Clock frequency
Symbol fCLK X'tal
Condition
Min. -500ppm -500ppm 40
Typ. 30 30 50
Max. +500ppm +500ppm 60
Unit MHz MHz %
Oscillator block Clock Duty cycle TDUTY
Remarks 1. 2.
Reccomended accurarcy of clock frequency is 100ppm. Required accurarcy of X'tal or Oscillator block is includeing initial frequency accuracy, the spread of X'tal capacityor loading, supply voltage, temperature, and aging etc.
(2) Reset
Symbol TR Reset width
Specification
Min. 2
Typ.
Max.
Unit
s
HW reset timing
RESETB
TR
20
Data Sheet S16685EJ2V0DS
PD720122
2.6.2 AC characteristics of BIU block with Function 1 selected
(1) CPU BUS read operation
Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Read cycle time Address setup time (RDB)
Parameter
Min. 91 5 5 - - 57 5 5 34 4
Typ.
Max. 14 57 -
Unit ns ns ns ns ns ns ns ns ns ns
Chip select setup time (RDB) Buffer direction change time (RDB) Output data delay time (RDB) Read command width Chip select hold time (RDB) Address hold time (RDB) RDB inactive time Output data hold time (RDB)
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
CPU bus read timing
t1
A7 to A1
VALID
t2
CSB
t8
t3
RDB
t6
t7 t9
WRB
High level
t5 t4
t10
High level
D15 to D0
INVALID
VALID
Data Sheet S16685EJ2V0DS
21
PD720122
(2) CPU bus write operation
Symbol T11 T12 T13 T14 T15 T16 T17 T18 T19 Write cycle time Address setup time (WRB)
Parameter
Min. 68 5 5 34 5 5 34 10 0
Typ.
Max.
Unit ns ns ns ns ns ns ns ns ns
Chip select setup time (WRB) Write command width Address hold time (WRB) Chip select hold time (WRB) WRB inactive time Input data setup time Input data hold time
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
CPU bus write timing
t11
A7 to A1 VALID
t12
CSB
t15
t13
WRB
t14
t16 t17
RDB D15 to D0
High level
t18
VALID
t19
22
Data Sheet S16685EJ2V0DS
PD720122
(3) CPU BUS RDB vs. WRB timing
Symbol T20 WRB vs. RDB inactive time
Parameter
Min. 34
Typ.
Max.
Unit ns
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
CPU bus read vs. write change timing
CSB
Low level
WRB t20
RDB
Data Sheet S16685EJ2V0DS
23
PD720122
(4) CPU bus DMA transfer
(a) CPU bus DMA single mode read transfer timing
Symbol T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34
Parameter DMA request acknowledge setup time (RDB) DMA request off time (EP1_DACKB) DMA single mode read transfer cycle time Read command width Read command inactive time Read data delay time (RDB) Buffer direction change time (RDB) Read data hold time (RDB) EP1_TCB setup time (RDB) EP1_TCB hold time (RDB) EP1_STOPB delay time (RDB) EP1_STOPB OFF delay time (RDB) DMA request acknowledge hold time (RDB) Undefined
Min. 0 - 91 57 34 - - 4 0 17 - 3 0 -
Typ.
Max. 54 57 14 - Note 15 - -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Can be input after previous RDB.
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall)
EP1_DRQB
t22
EP1_DACKB
t21
RDB
t33 t24
t23 t25 t28
t26
D15 to D0
1 cycle
N - 1 cycle
N cycle
t27
EP1_TCB EP1_STOPB High level High level
EP1_STOPB is not asserted in the case of a full packet.
t31
t32
24
Data Sheet S16685EJ2V0DS
PD720122
(Start timing)
EP1_DRQB
t22
EP1_DACKB
t21
RDB
t24
t33
t25
t23 t26
D15 to D0
VALID
t28
VALID
t27
EP1_TCB High level
EP1_STOPB
High level
(End timing)
EP1_DRQB
EP1_DACKB
t22 t33
RDB
Last - 1
Last
D15 to D0
VALID
VALID
EP1_TCB EP1_STOPB
High level High level
t31
t32
EP1_STOPB is not asserted in the case of a full packet.
Data Sheet S16685EJ2V0DS
25
PD720122
(TCB timing)
t22
EP1_DRQB
EP1_DACKB
t21
RDB
t29
EP1_TCB
t30
26
Data Sheet S16685EJ2V0DS
PD720122
(b) CPU bus DMA single mode write transfer
Symbol T35 T36 T37 T38 T39 T40 T41 T42 T43 T44
Parameter DMA request acknowledge setup time (WRB) DMA request off time (EP2_DACKB) DMA single mode write transfer cycle time Write command width Write command inactive time Write data setup time (WRB) Write data hold time (WRB) EP2_TCB setup time (WRB) EP2_TCB hold time (WRB) DMA request acknowledge hold time (WRB)
Min. 0 - 88 54 34 10 0 0 17 0
Typ.
Max. 54 Note
Unit ns ns ns ns ns ns ns ns ns ns
Note
Can be input after immediately previous WRB.
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall)
EP2_DRQB
t36
EP2_DACKB
t35
WRB
t37 t38 t40
t44
t44
t39 t41 t40 t41
N cycle
D15 to D0
1 cycle
N - 1 cycle
EP2_TCB
High level
Data Sheet S16685EJ2V0DS
27
PD720122
(Start timing)
EP2_DRQB
t36
EP2_DACKB
t35 t38
WRB
t44 t39
t37
D15 to D0
t40
VALID
t41
VALID
EP2_TCB
High level
(End timing)
EP2_DRQB
t36
EP2_DACKB
t44
WRB Last - 1 Last
t40
D15 to D0 VALID
t41
VALID
EP2_TCB
High level
28
Data Sheet S16685EJ2V0DS
PD720122
(TCB timing)
t36
EP2_DRQB
EP2_DACKB
t35
WRB
t42
EP2_TCB
t43
Data Sheet S16685EJ2V0DS
29
PD720122
(c) CPU bus DMA demand read transfer timing
Symbol T45 T46 T47 T48 T49 T50 T51 T52 T53 T54 T55 T56 T57 T69 T71 T72 T74 Parameter DMA request acknowledge setup time (RDB) DMA demand mode read transfer cycle time Read command width Read command inactive time Read data delay time (RDB) Buffer direction change time (RDB) Read data hold time (RDB) EP1_TCB setup time (RDB) EP1_TCB hold time (RDB) EP1_STOPB delay time (RDB) EP1_STOPB delay time (RDB) DMA request off time (RDB) DMA request acknowledge hold time (RDB) DMA request off time (EP1_DACKB) DMA request off time (EP1_DACKB) 1 cycle transfer DMA request on time (EP1_DACKB) DMA request off time (RDB) Min. 0 91 57 34 - - 4 0 17 - 3 - 0 - - - - Typ. Max. 57 14 - Note 15 - 59 38 38 88 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Can be input after immediately previous RDB.
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall)
EP1_DRQB
t56
EP1_DACKB
t45 t47
RDB
t46 t48 t57
t49 t50
D15 to D0 1 cycle
t51
N - 1 cycle
N cycle
EP1_TCB
High level High level
t54
t55
EP1_STOPB
EP1_STOPB is not asserted in the case of a full packet.
30
Data Sheet S16685EJ2V0DS
PD720122
(Start timing)
EP1_DRQB
EP1_DACKB
t45
RDB
t47
t48
t49 t50
t51
VALID VALID
D15 to D0 EP1_TCB High level
(End timing)
EP1_DRQB
t56
EP1_DACKB
t57
RDB Last - 1 Last
D15 to D0
VALID
VALID
EP1_TCB
High level
t54
t55
EP1_STOPB
High level
EP1_STOPB is not asserted in the case of a full packet.
Data Sheet S16685EJ2V0DS
31
PD720122
(TCB timing)
t74
EP1_DRQB
EP1_DACKB
RDB
t52
EP1_TCB
t53
(Retransmission timing)
DMA transfer retry timing If EP1_DACKB is deasserted without RDB access after EP1_DRQB has been deasserted, EP1_DRQB is asserted again.
t72
EP1_DRQB
t56
EP1_DACKB
t69
RDB
Last - 1
Last
D15 to D0
VALID
VALID
EP1_TCB EP1_STOPB
High level
t54
t55
High level
EP1_STOPB is not asserted in the case of a full packet.
32
Data Sheet S16685EJ2V0DS
PD720122
(If EP1_TCB is input when retransmission is executed)
t69
EP1_DRQB
EP1_DACKB
t45
RDB
t52
EP1_TCB
t53
(One-cycle transfer)
EP1_DRQB
t71
EP1_DACKB
t45
RDB
t47
t49 t50
t51
VALID
D15 to D0
EP1_TCB
High level
t54
EP1_STOPB
t55
Data Sheet S16685EJ2V0DS
33
PD720122
(d) CPU bus DMA demand write transfer timing
Symbol T58 T59 T60 T61 T62 T63 T64 T65 T66 T67 T70 T73 T75
Parameter DMA request acknowledge setup time (WRB) DMA demand mode write transfer cycle time Write command width Write command inactive time Write data setup time (WRB) Write data hold time (WRB) EP2_TCB setup time (WRB) EP2_TCB hold time (WRB) DMA request off time (WRB) DMA request acknowledge hold time (WRB) DMA request off time (EP2_DACKB) DMA request on time (EP2_DACKB) DMA request off time (WRB)
Min. 0 72 38 34 10 0 0 17 - 0 - - -
Typ.
Max. Note 60 38 88 60
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Can be input after immediately previous WRB.
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall)
EP2_DRQB
EP2_DACKB
t66 t58 t60 t59 t61 t67
WRB
t62
t63
N - 1 cycle
D15 to D0
1 cycle
N cycle
EP2_TCB
High level
34
Data Sheet S16685EJ2V0DS
PD720122
(Start timing)
EP2_DRQB
EP2_DACKB
t58
WRB
t60
t61
t62
D15 to D0
t63
VALID
VALID
EP2_TCB
High level
(End timing)
t66
EP2_DRQB
t67
EP2_DACKB
WRB
Last - 1
Last
t62
D15 to D0 VALID
t63
VALID
EP2_TCB
Data Sheet S16685EJ2V0DS
35
PD720122
(TCB timing)
t75
EP2_DRQB
EP2_DACKB
WRB
t64
EP2_TCB
t65
(Retransmission timing)
DMA transfer retry timing If EP2_DACKB is deasserted without WRB access after EP2_DRQB has been deasserted, EP2_DRQB is asserted again.
t73
EP2_DRQB
EP2_DACKB
t66
t70
WRB
Last - 1
Last
t62
D15 to D0 VALID
t63
VALID
EP2_TCB
High level
36
Data Sheet S16685EJ2V0DS
PD720122
(If EP1_TCB is input when retransmission is executed)
t70
EP2_DRQB
EP2_DACKB
t58
WRB
t64
EP2_TCB
t65
Data Sheet S16685EJ2V0DS
37
PD720122
(a) CPU bus DMA read transfer vs. write transfer timing
Symbol T68
Parameter RDB vs. WRB command inactive time
Min. 34
Typ.
Max.
Unit ns
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
EP1_DRQB
Low level
EP1_DACKB
t45
RDB
t57
Low level EP2_DRQB
EP2_DACKB
t68
WRB
t58
38
Data Sheet S16685EJ2V0DS
PD720122
2.6.3 AC characteristics of BIU block with function 2 or 3 selected
(1) CPU bus read operation
Symbol TB1 TB2 TB3 TB4 TB5 TB6 TB7 TB8 TB9 TB10 TB11 TB12 Read cycle time Address setup time (ALE)
Parameter
Min. 86 10 17 7 - 57 4 5 10 0 5 -
Typ.
Max. 57 - 14
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Chip select setup time (ALE) Read command delay time (ALE) Output data delay time (RDB) Read command width Output data hold time (RDB) Chip select hold time (RDB) ALE width Address hold time (ALE) Chip select setup time (RDB) Buffer direction change time (RDB)
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
CPU bus read timing
DATA invalid
DATA VALID ADDRES VALID
tb1
AD7 to AD0Note D15 to D8
ADDRES VALID
tb2
ALE
tb12 tb5
tb9 tb3
tb10
tb7
tb8 tb11 tb4 tb6
CSB
RDB
Note
D7 to D0 for Function 2
Data Sheet S16685EJ2V0DS
39
PD720122
(2) CPU bus write operation
Symbol TB13 TB14 TB15 TB16 TB17 TB18 TB19 TB20 TB21 Write cycle time Address setup time (ALE)
Parameter
Min. 58 17 17 7 10 0 34 0 5
Typ.
Max.
Unit ns ns ns ns ns ns ns ns ns
Chip select setup time (ALE) Write command delay time (ALE) Input data setup time (WRB) Input data hold time (WRB) Write command width Chip select hold time (WRB) Chip select setup time (WRB)
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
CPU bus write timing tb13
AD7 to AD0Note D15 to D8
ADDRESS VALID DATA VALID ADDRESS VALID
tb2 tb10
ALE
tb17
tb18
tb9 tb15
CSB
tb21 tb16
tb20
WRB
tb19
Note
D7 to D0 for Function 2
40
Data Sheet S16685EJ2V0DS
PD720122
2.6.4 External local bus
(1) External local bus 16-bit mode
(a) External local bus 16-bit mode DMA single mode read transfer timing
Symbol L16T21 L16T22 L16T23 L16T24 L16T25 L16T26 L16T27 L16T28 L16T29 L16T30 L16T31 L16T32 L16T33 L16T34
Parameter DMA request acknowledge setup time (EP1_RDB) DMA request off time 1 (EP1_DACKB) DMA single mode read transfer cycle time Read command width Read command inactive time Read data delay time (EP1_RDB) Buffer direction change time (EP1_RDB) Read data hold time (EP1_RDB) EP1_TCB setup time (EP1_RDB) EP1_TCB hold time (EP1_RDB) EP1_STOPB delay time (EP1_RDB) EP1_STOPB delay time (EP1_RDB) DMA request acknowledge hold time (EP1_RDB) Undefined
Min. 0 - 91 57 34 - - 4 0 17 - 3 0 -
Typ.
Max. 54 57 14 - Note 15 - -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Can be input after previous EP1_RDB.
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
Data Sheet S16685EJ2V0DS
41
PD720122
(Overall) L16t22
EP1_DRQB
L16t21 L16t33
EP1_DACKB
L16t24
EP1_RDB
L16t25
L16t23 L16t26
LD15 to LD0
1 cycle
L16t28
N - 1 cycle
N cycle
L16t27
EP1_TCB
High level
L16t31
EP1_STOPB High level
L16t32
EP1_STOPB is not asserted in the case of a full packet.
(Start timing) L16t22
EP1_DRQB
L16t21
EP1_DACKB
L16t33
L16t24
EP1_RDB
L16t25 L16t23
L16t26
LD15 to LD0 VALID
L16t28
VALID
L16t27
EP1_TCB High level
42
Data Sheet S16685EJ2V0DS
PD720122
(End timing)
L16t22
EP1_DRQB
L16t33
EP1_DACKB
EP1_RDB
Last - 1
Last
LD15 to LD0
VALID
VALID
EP1_TCB
High level
L16t31
L16t32
EP1_STOPB
High level
EP1_STOPB is not asserted in the case of a full packet.
(TCB timing)
L16T22
EP1_DRQB
EP1_DACKB
L16T21
EP1_RDB
L16T29
EP1_TCB
L16T30
Data Sheet S16685EJ2V0DS
43
PD720122
(a) External local bus 16-bit mode DMA single mode write transfer
Symbol L16T35 L16T36 L16T37 L16T38 L16T39 L16T40 L16T41 L16T42 L16T43 L16T44
Parameter DMA request acknowledge setup time (EP2_WRB) DMA request off time 1 (EP2_DACKB) DMA single mode write transfer cycle time Write command width Write command inactive time Write data setup time (EP2_WRB) Write data hold time (EP2_WRB) EP2_TCB setup time (EP2_WRB) EP2_TCB hold time (EP2_WRB) DMA request acknowledge hold time (EP2_WRB)
Min. 0 - 88 54 34 10 0 0 17 0
Typ.
Max. 54 Note
Unit ns ns ns ns ns ns ns ns ns ns
Note
Can be input after previous EP2_WRB.
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall) L16t36
EP2_DRQB
L16t35
EP2_DACKB
L16t44
L16t37 L16t38
EP2_WRB
L16t39
L16t40 L16t40
LD15 to LD0
1 cycle
L16t41
L16t41
N - 1 cycle
N cycle
EP2_TCB
High level
44
Data Sheet S16685EJ2V0DS
PD720122
(Start timing) L16t36
EP2_DRQB
EP2_DACKB
L16t35 L16t38
EP2_WRB
L16t44 L16t39 L16t37 L16t40 L16t41
VALID
LD15 to LD0
VALID
EP2_TCB
High level
(End timing)
L16t36
EP2_DRQB
EP2_DACKB
L16t44
EP2_WRB Last - 1 Last
L16t40
LD15 to LD0 VALID
L16t41
VALID
EP2_TCB
High level
Data Sheet S16685EJ2V0DS
45
PD720122
(TCB timing)
L16t36
EP2_DRQB
EP2_DACKB
L16t35
EP2_WRB
EP2_TCB
L16t42
L16t43
46
Data Sheet S16685EJ2V0DS
PD720122
(c) External local bus 16-bit mode DMA demand read transfer timing
Symbol L16T45 L16T46 L16T47 L16T48 L16T49 L16T50 L16T51 L16T52 L16T53 L16T54 L16T55 L16T56 L16T57 L16T69 L16T71 L16T72 L16T74
Parameter DMA request acknowledge setup time (EP1_RDB) DMA demand mode read transfer cycle time Read command width Read command inactive time Read data delay time (EP1_RDB) Buffer direction change time (EP1_RDB) Read data hold time (EP1_RDB) EP1_TCB setup time (EP1_RDB) EP1_TCB hold time (EP1_RDB) EP1_STOPB delay time (EP1_RDB) EP1_STOPB delay time (EP1_RDB) DMA request off time (EP1_RDB) DMA request acknowledge hold time (EP1_RDB) DMA request off time (EP1_DACKB) DMA request off time (EP1_DACKB) 1 cycle transfer DMA request on time (EP1_DACKB) DMA request off time (EP1_RDB)
Min. 0 91 57 34 - - 4 0 17 - 3 - 0 - - - -
Typ.
Max. 57 14 - Note 15 - 59 38 38 88 60
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Can be input after immediately previous EP1_RDB.
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
Data Sheet S16685EJ2V0DS
47
PD720122
(Overall)
EP1_DRQB
L16t56
EP1_DACKB
L16t46 L16t45
EP1_RDB
L16t47
L16t48
L16t57
L16t49
LD15 to LD0
L16t51
N - 1 cycle
1 cycle
N cycle
L16t50
EP1_TCB
High Level
L16t54
L16t55
EP1_STOPB
High Level EP1_STOPB is not asserted in the case of a full packet.
(Start timing)
EP1_DRQB
EP1_DACKB
L16t45
EP1_RDB
L16t47
L16t48
L16t46 L16t49 L16t50
LD15 to LD0 VALID VALID
L16t51
EP1_TCB
High level
48
Data Sheet S16685EJ2V0DS
PD720122
(End timing)
EP1_DRQB EP1_DACKB
L16t56 L16t57
EP1_RDB
Last - 1
Last
LD15 to LD0
VALID
VALID
EP1_TCB
High level
L16t54
EP1_STOPB High level
L16t55
EP1_STOPB is not asserted in the case of a full packet.
(TCB timing)
L16t74
EP1_DRQB
EP1_DACKB
EP1_RDB
L16t52
EP1_TCB
L16t53
Data Sheet S16685EJ2V0DS
49
PD720122
(Retransmission timing)
DMA transfer retry timing If EP1_DACKB is deasserted without RDB access after EP1_DRQB has been deasserted, EP1_DRQB is asserted again. However, note that the retry operation cannot be performed in the 8-bit mode.
L16t72
EP1_DRQB
L16t56
EP1_DACKB
L16t69
EP1_RDB
Last - 1
Last
LD15 to LD0
VALID
VALID
EP1_TCB EP1_STOPB
High level
L16t54
L16t55
High level
EP1_STOPB is not asserted in the case of a full packet.
(If EP1_TCB is input when retransmission is executed)
L16t69
EP1_DRQB
L16t45
EP1_DACKB
EP1_RDB
L16t52
EP1_TCB
L16t53
50
Data Sheet S16685EJ2V0DS
PD720122
(One-cycle transfer)
EP1_DRQB
L16t71
EP1_DACKB
L16t45
EP1_RDB
L16t47
L16t50
LD15 to LD0
L16t49 L16t51
VALID
EP1_TCB EP1_STOPB
High level
L16t54
L16t55
Data Sheet S16685EJ2V0DS
51
PD720122
(d) External local bus 16-bit mode DMA demand write transfer timing
Symbol L16T58 L16T59 L16T60 L16T61 L16T62 L16T63 L16T64 L16T65 L16T66 L16T67 L16T70 L16T73 L16T75
Parameter DMA request acknowledge setup time (EP2_WRB) DMA demand mode write transfer cycle time Write command width Write command inactive time Write data setup time (EP2_WRB) Write data hold time (EP2_WRB) EP2_TCB setup time (EP2_WRB) EP2_TCB hold time (EP2_WRB) DMA request off time (EP2_WRB) DMA request acknowledge hold time (EP2_WRB) DMA request off time (EP2_DACKB) DMA request on time (EP2_DACKB) DMA request off time (EP2_WRB)
Min. 0 72 38 34 10 0 0 17 - 0 - - -
Typ.
Max. Note 60 38 88 60
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Can be input after previous EP2_WRB.
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall)
EP2_DRQB
EP2_DACKB
L16t66 L16t59 L16t58 L16t60 L16t61 L16t67
EP2_WRB
L16t62
LD15 to LD0
1 cycle
L16t63
N - 1 cycle
N cycle
EP2_TCB High level
52
Data Sheet S16685EJ2V0DS
PD720122
(Start timing)
EP2_DRQB
EP2_DACKB
L16t58 L16t59 L16t60 L16t62 L16t61 L16t63
EP2_WRB
LD15 to LD0
VALID
VALID
EP2_TCB
High level
(End timing) L16t66
EP2_DRQB
L16t67
EP2_DACKB
EP2_WRB
Last - 1
Last
L16t62
LD15 to LD0
L16t63
VALID
VALID
EP2_TCB
High level
Data Sheet S16685EJ2V0DS
53
PD720122
(TCB timing)
L16t75
EP2_DRQB
EP2_DACKB
EP2_WRB
L16t64
EP2_TCB
L16t65
(Retransmission timing)
DMA transfer retry timing If EP2_DACKB is deasserted without RDB access after EP2_DRQB has been deasserted, EP2_DRQB is asserted again. However, note that the retry operation cannot be performed in the 8-bit mode.
L16t73
EP2_DRQB
L16t70 L16t66
EP2_DACKB
EP2_WRB
Last - 1
L16t62 L16t63
Last
LD15 to LD0
VALID
VALID
EP2_TCB
High level
54
Data Sheet S16685EJ2V0DS
PD720122
(If EP1_TCB is input when retransmission is executed)
L16t70
EP2_DRQB
EP2_DACKB
L16t58
EP2_WRB
L16t64
EP2_TCB
L16t65
(e) External local bus 16-bit mode DMA EP1_Read transfer vs. EP2_Write transfer timing
Symbol L16T68
Parameter EP1_RDB vs. EP2_WRB command inactive time
Min. 34
Typ.
Max.
Unit ns
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
EP1_DRQB Low level
EP1_DACKB
L16t45
EP1_RDB
L16t57
EP2_DRQB
Low level
EP2_DACKB
L16t68
EP2_WRB
L16t58
Data Sheet S16685EJ2V0DS
55
PD720122
(2) External local bus 8-bit mode
(a) External local bus 8-bit mode DMA single mode read transfer timing
Symbol L8T21 L8T22 L8T23 L8T24 L8T25 L8T26 L8T27 L8T28 L8T31 L8T32 L8T33 L8T34
Parameter DMA request acknowledge setup time (EP1_RDB) DMA request off time 1 (EP1_DACKB) DMA single mode read transfer cycle time Read command width Read command inactive time Read data delay time (EP1_RDB) Buffer direction change time (EP1_RDB) Read data hold time (EP1_RDB) EP1_STOPB delay time (EP1_RDB) EP1_STOPB delay time (EP1_RDB) DMA request acknowledge hold time (EP1_RDB) Undefined
Min. 0 - 91 57 34 - - 4 - 3 0 -
Typ.
Max. 10 57 14 - 15 - -
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. 2. 3.
Use of EP1_TCB is prohibited in the 8-bit external local bus mode. Clamp this signal to the inactive status. LD15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall)
EP1_DRQB
L8t22
EP1_DACKB
L8t21
EP1_RDB
L8t23 L8t24 L8t25 L8t28
1 cycle
N - 1 cycle
L8t33
L8t26
LD7 to LD0
N cycle
L8t27
EP1_TCB EP1_STOPB High level High level
EP1_STOPB is not asserted in the case of a full packet.
L8t31
L8t32
56
Data Sheet S16685EJ2V0DS
PD720122
(Start timing)
EP1_DRQB
L8t22
EP1_DACKB
L8t21
L8t33 L8t23 L8t24
EP1_RDB
L8t25 L8t28
VALID VALID
L8t26
LD7 to LD0
L8t27
EP1_TCB High level
(End timing)
EP1_DRQB
L8t22
EP1_DACKB
L8t33
EP1_RDB
Last - 1
Last
LD7 to LD0
VALID
VALID
EP1_TCB
High level
L8t31
L8t32
EP1_STOPB
High level
EP1_STOPB is not asserted in the case of a full packet.
Data Sheet S16685EJ2V0DS
57
PD720122
(b) External local bus 8-bit mode DMA single mode write transfer
Symbol L8T35 L8T36 L8T37 L8T38 L8T39 L8T40 L8T41 L8T44
Parameter DMA request acknowledge setup time (EP2_WRB) DMA request off time 1 (EP2_DACKB) DMA single mode write transfer cycle time Write command width Write command inactive time Write data setup time (EP2_WRB) Write data hold time (EP2_WRB) DMA request acknowledge hold time (EP2_WRB)
Min. 0 - 88 54 34 10 0 0
Typ.
Max. 54
Note
Unit ns ns ns ns ns ns ns ns

Remarks 1. 2. 3.
Use of EP1_TCB is prohibited in the 8-bit external local bus mode. Clamp this signal to the inactive status. LD15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
Note
The difference in specifications when compared with L8T22 is that BIU processing is performed for EP1 and that EPC2 processing is performed for EP2.
(Overall)
EP2_DRQB
L8t36
EP2_DACKB
L8t44 L8t35
L8t37 L8t39
EP2_WRB
L8t44 L8t38
L8t40
LD7 to LD0
1 cycle
L8t41
L8t40
N - 1 cycle
L8t41
N cycle
EP2_TCB
High Level
58
Data Sheet S16685EJ2V0DS
PD720122
(Start timing)
EP2_DRQB
L8t36
EP2_DACKB
L8t35
L8t44 L8t37 L8t38 L8t39
EP2_WRB
L8t40 L8t41
LD7 to LD0 VALID VALID
EP2_TCB
High level
(End timing)
EP2_DRQB
L8t36
EP2_DACKB
L8t44
EP2_WRB Last - 1 Last
L8t40
LD7 to LD0 VALID
L8t41
VALID
EP2_TCB
High level
Data Sheet S16685EJ2V0DS
59
PD720122
(c) External local bus 8-bit mode DMA demand read transfer timing
Symbol L8T45 L8T46 L8T47 L8T48 L8T49 L8T50 L8T51 L8T54 L8T55 L8T56 L8T57
Parameter DMA request acknowledge setup time (EP1_RDB) DMA demand mode read transfer cycle time Read command width Read command inactive time Read data delay time (EP1_RDB) Buffer direction change time (EP1_RDB) Read data hold time (EP1_RDB) EP1_STOPB delay time (EP1_RDB) EP1_STOPB delay time (EP1_RDB) DMA request off time (EP1_RDB) DMA request acknowledge hold time (EP1_RDB)
Min. 0 90 56 34 - - 4 - 3 - 0
Typ.
Max. 56 14 - 15 - 60
Unit ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. 2. 3.
Use of EP1_TCB is prohibited in the 8-bit external local bus mode. Clamp this signal to the inactive status. LD15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall)
EP1_DRQB
L8t45
EP1_DACKB
L8t56 L8t57
L8t46 L8t47
EP1_RDB
L8t48
L8t49
LD7 to LD0
1 cycle
L8t51
N - 1 cycle
N cycle
L8t50
EP1_TCB EP1_STOPB
High level High level
L8t54
L8t55
EP1_STOPB is not asserted in the case of a full Packet.
60
Data Sheet S16685EJ2V0DS
PD720122
(Start timing)
EP1_DRQB
L8t45
EP1_DACKB
L8t47
EP1_RDB
L8t48
L8t49 L8t51 L8t50
VALID LD7 to LD0 VALID
EP1_TCB
High level
(End timing)
EP1_DRQB
L8t56
EP1_DACKB
L8t57
EP1_RDB
Last - 1
Last
LD7 to LD0
VALID
VALID
EP1_TCB
High level
L8t54
L8t55
EP1_STOPB
High level
EP1_STOPB is not asserted in the case of a full packet.
Data Sheet S16685EJ2V0DS
61
PD720122
(d) External local bus 8-bit mode DMA demand write transfer timing
Symbol L8T58 L8T59 L8T60 L8T61 L8T62 L8T63 L8T66 L8T67
Parameter DMA request acknowledge setup time (EP2_WRB) DMA demand mode write transfer cycle time Write command width Write command inactive time Write data setup time (EP2_WRB) Write data hold time (EP2_WRB) DMA request off time (EP2_WRB) DMA request acknowledge hold time (EP2_WRB)
Min. 0 72 38 34 10 0 - 0
Typ.
Max. 60
Unit ns ns ns ns ns ns ns ns
Remarks 1. 2. 3.
Use of EP1_TCB is prohibited in the 8-bit external local bus mode. Clamp this signal to the inactive status. LD15 to 8 are undefined in the 8-bit external local bus mode (these signals are invalid when input and undefined when output). It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall)
EP2_DRQB
L8t67
EP2_DACKB
L8t66 L8t59 L8t58 L8t60 L8t61
EP2_WRB
L8t62
LD7 to LD0 1 cycle
L8t63
L8t62
N - 1 cycle
L8t63
N cycle
EP2_TCB
High level
62
Data Sheet S16685EJ2V0DS
PD720122
(Start timing)
EP2_DRQB
L8t58
EP2_DACKB
L8t59 L8t60
EP2_WRB
L8t61 L8t63
VALID
L8t62
LD7 to LD0 VALID
EP2_TCB
High level
(End timing) L8t66
EP2_DRQB
L8t67
EP2_DACKB
EP2_WRB
Last - 1
Last
L8t62
LD7 to LD0 VALID
L8t63
VALID
EP2_TCB
Data Sheet S16685EJ2V0DS
63
PD720122
(e) External local bus 8-bit mode DMA EP1_Read transfer vs. EP2_Write transfer timing
Symbol L8T68
Parameter EP1_RDB vs. EP2_WRB command inactive time
Min. 34
Typ.
Max.
Unit ns
Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
EP1_DRQB Low level
EP1_DACKB
L8t45
EP1_RDB EP2_DRQB Low level
L8t57
EP2_DACKB
L8t68
EP2_WRB
L8t58
64
Data Sheet S16685EJ2V0DS
PD720122
2.6.5 USB interface timing
Parameter Full-speed source electrical characteristics Rise time Fall time Differential rise and fall time matching Full-speed data rate for hubs and devices that are high-speed capable Frame interval Consecutive frame interval jitter Source jitter total (including frequency tolerance): To next transition For paired transitions Source jitter for differential transition to SE0 transition Receiver jitter: To next transition For paired transitions Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition
Symbol
Conditions
Min.
Max.
Unit
TFR TFF TFRFM TFDRATHS TFRAME TRFI
CL = 50 pF, RS = 36 CL = 50 pF, RS = 36 (TFR/TFF) Average bit rate
4 4 90 11.9940 0.9995
20 20 111.11 12.0060 1.0005 42
ns ns % Mb/s ms ns
No clock adjustment
TDJ1 TDJ2 TFDEOP
-3.5 -4.0 -2
3.5 4.0 5
ns ns ns
TJR1 TJR2 TFEOPT TFEOPR TFST
-18.5 -9 160 82
18.5 9 175
ns ns ns ns
14
ns
High-speed source electrical characteristics Rise time (10% to 90%) Fall time (10% to 90%) Driver waveform requirements High-speed data rate Microframe interval Consecutive microframe interval difference Data source jitter Receiver jitter tolerance THSR THSF See Figure 2-6 THSDRAT THSFRAM THSRFI See Figure 2-6. See Figure 2-4. 479.760 124.9375 480.240 125.0625 4 high-speed Mb/s 500 500 ps ps
s
Bit times
Data Sheet S16685EJ2V0DS
65
PD720122
Parameter Device event timing Time from internal power good to device pulling D+/D- beyond VIHZ (min.) (signaling attach) Debounce interval provided by USB system software after attach Inter-packet delay (for low-/full-speed) Inter-packet delay for device response w/detachable cable for low-/full-speed High-speed detection start time from suspend Sample time for suspend vs. reset Power down under suspend SUSPEND set time (SPNDOUT) SUSPEND clear time (RSUMOUT) Reversion time from suspend to high-speed SUSPEND setup time (RSUMIN) RSUMIN active pulse width Drive chirp K width Finish chirp K assertion Start sequencing chirp K-J-K-J-K-J Finish sequencing chirp K-J Detect sequencing chirp K-J width Sample time for sequencing chirp Reversion time to high-speed High-speed detection start time Reset completed time TATTDB TIPD TRSPIPD1 TSCA TCSR TSUS TSSP TCSP TRHS TSRW TRWP TCKO TFCA TSSC TFSC TCSI TSCS TRHA THDS TDRS 2.5 10 -500 2.5 1.0 2.5 500 3000 0 1 1 7 100 -100 0 0 2.5 100 875 10 - - 1.333 - 15 ms ms ms 2 6.5 100 ms Bit times Bit times TSIGATT 100 ms Symbol Conditions Min. Max. Unit
s s
ms
s
s s s
ms
s s
ms
66
Data Sheet S16685EJ2V0DS
PD720122
Figure 2-6. Transmit Waveform for Transceiver at D+/D- -
Level 1
+400 mV differential
Point 3 Point 4
Point 1
Point 2
0V differential
Point 5 Level 2
Point 6
-400 mV differential
Unit interval 0% 100%
Figure 2-7. Transmitter Measurement Fixtures
Test supply voltage 15.8 USB connector nearest device Vbus D+ D- Gnd 50 Coax 50 Coax + To 50- input of a high-speed differential oscilloscope, or 50- output of a high speed differential data generator -
15.8
143
143
Data Sheet S16685EJ2V0DS
67
PD720122
(1) Power-on and connection events
Figure 2-8. Power-on and Connection Event Timing
Hub port power OK Hub port power-on VBUS VIH(min) VIH D+ or D- t1
Attach detected
Reset recovery time
4.01 V
t4
t5
USB system software reads device speed
100 ms TSIGATT
10 ms 100 ms TATTDB t6
(2) USB signals
Figure 2-9. USB Differential Data Jitter for Full-Speed
TPERIOD Differential data lines
Crossover points
Consecutive transitions N * TPERIOD + TxDJ1 Paired transitions N * TPERIOD + TxDJ2
68
Data Sheet S16685EJ2V0DS
PD720122
Figure 2-10. USB Differential-to-EOP Transition Skew and EOP Width for Full-Speed
TPERIOD Differential data lines
Crossover point
Crossover point extended
Diff. Data-toSE0 skew N * TPERIOD + TxDEOP
Source EOP width:
TFEOPT TLEOPT
Receiver EOP width: TFEOPR, TLEOPR
Data Sheet S16685EJ2V0DS
69
PD720122
Figure 2-11. USB Receiver Jitter Tolerance for Full-Speed
TPERIOD Differential data lines
TxJR TxJR1 TxJR2
Consecutive transitions N * TPERIOD + TxJR1 Paired transitions N * TPERIOD + TxJR2
(3) USB connection sequence on USB1.1 bus The PHY core implemented on the PD720122 automatically determines the Up port. Check the SP_MODE bit (SP_MODE) of the Int Status 2 register after an EPC2_STG bus reset interrupt has occurred to determine whether the USB is connected to FS or HS.
Figure 2-12. USB Connection Sequence on USB 1.1 Bus
USB bus
Pull-up is active. FS J tHDS tFCA tSCA
Chirp K device out
Reversion to full-speed mode FS J
tCKO tCKI
tSCS
tDRS T0
USBRST SPMODE High
70
Data Sheet S16685EJ2V0DS
PD720122
(4) USB connection sequence on USB 2.0 bus
Figure 2-13. USB Connection Sequence on USB 2.0 Bus
Chirp state from host/hub Chirp K device out
Pull-up is active.
Reversion to high-speed mode
USB bus
FS J
K tHDS tFCA tSCA tCKO tCKI tSSC tCSO tCSI
J
K
J
K
J
K
J tRHA
Reset Complete
tSCS
tFSC
T0 USBRST
SPMODE
(5) Bus reset sequence (1) The bus reset sequence when connected to a USB 1.1 bus is shown below.
Figure 2-14. Bus Reset Sequence (1)
Pull-up is inactive. High-speed packet
Reversion to full-speed mode
Chirp K device out
USB bus tSPD tCSR tFCA tDRS T0 USBRST tSCA tCKO tCKI tSCS
FS J
SPMODE
Data Sheet S16685EJ2V0DS
71
PD720122
(6) Bus reset sequence (2) The bus reset sequence when connected to a USB 2.0 bus is shown below.
Figure 2-15. Bus Reset Sequence (2)
Reversion to high-speed mode J K J Reset Complete
Pull-up is inactive High-speed packet
Reversion to full-speed mode
Chirp K device out K
Chirp state from host/hub J K J K
USB bus tSPD tCSR tFCA tSCA tCKO tCKI tSSC
tCSO tCSI tSCS
tRHA tFSC
T0 USBRST
SPMODE
72
Data Sheet S16685EJ2V0DS
PD720122
(7) USB reset from suspend state (1)
Figure 2-16. USB Reset from Suspend State (1)
USB bus
Pull-up is active. FS J
Chirp K device out FS J
tSCA tFCA
tCKO tCKI
tSCS
tDRS
T0
USB_RST SPMODE
(8) USB reset from suspend state (2)
Figure 2-17. USB Reset from Suspend State (2)
Reversion to high-speed mode J K J tRHA tSCS tFSC Reset Complete
Pull-up is inactive. USB bus
FS J
Chirp K device out K tSCA tFCA tCKO tCKI tSSC tCSO tCSI
Chirp state from host/hub J K J K
T0 USBRST
SPMODE
Data Sheet S16685EJ2V0DS
73
PD720122
(9) Suspend and resume on USB1.1 bus
Figure 2-18. Suspend and Resume on USB 1.1 Bus
FS EOP USB bus tSPD tSUS SPNDOUT FS J Current source and PLL, etc. are disabled. FS K FS J
SUSPEND tSSP RSUMOUT tCSP SPMODE High Note time required to relock PLL and stabilize oscillator.
74
Data Sheet S16685EJ2V0DS
PD720122
(10) Suspend and resume on USB2.0 bus
Figure 2-19. Suspend and Resume on USB 2.0 Bus
Reversion to full-speed mode High-speed packet USB bus tSPD tCSR tSUS T0 SPNDOUT FS J Current source and PLL, etc. are disabled. FS K
Reversion to high-speed mode High-speed packet
tRHS
SUSPEND tSSP RSUMOUT tCSP Low SPMODE Note time required to relock PLL and stabilize oscillator.
(11) Remote wakeup on USB1.1
Figure 2-20. Remote Wakeup on USB 1.1
FS EOP USB bus tSPD tSUS SPNDOUT FS J FS K FS J
SUSPEND tSSP RSUMOUT
Current source and PLL, etc. are disabled. RSUMIN tRWP SPMODE High tSRW
Data Sheet S16685EJ2V0DS
75
PD720122
(12) Remote wakeup on USB2.0
Figure 2-21. Remote Wakeup on USB 2.0
Reversion to full-speed mode High-speed packet USB bus tSPD T0 SPNDOUT tCSR tSUS FS J FS K tRHS Reversion to high-speed mode High-speed packet
SUSPEND tSSP RSUMOUT
Current source and PLL, etc. are disabled. RSUMIN tRWP SPEEDMODE Low tSRW
76
Data Sheet S16685EJ2V0DS
PD720122
3. PACKAGE DRAWING
100-PIN PLASTIC TQFP (FINE PITCH) (14x14)
A B
75 76 51 50
detail of lead end S C D P T
R
100 1 26 25
L U
F G H I
M
Q J K S N S M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 16.00.2 14.00.2 14.00.2 16.00.2 1.0 1.0 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.08 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P100GC-50-9EU
Data Sheet S16685EJ2V0DS
77
PD720122
109-PIN PLASTIC FBGA (11x11)
D ZE ZD A
wSA
B E
12 11 10 9 8 7 6 5 4 3 2 1 ML K J HGFEDCBA
INDEX MARK
wSB
(UNIT:mm) ITEM D E w A A1 A2 e DIMENSIONS 11.000.10 11.000.10 0.20 1.280.10 0.350.06 0.93 0.80 0.50 +0.05 -0.10 0.08 0.10 0.20 1.10 1.10 P109F1-80-DN2
A y1 S A2 S
y
S
e
A1
b x
b
x
M
S AB
y y1 ZD ZE
78
Data Sheet S16685EJ2V0DS
PD720122
4. RECOMMENDED SOLDERING CONDITIONS
The PD720122 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
* PD720122GC-9EU : 100-pin plastic TQFP (Fine pitch) (14 x 14)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Exposure limit: 3 daysNote (after that, prebake at 125C for 10 hours) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Symbol IR35-103-2
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
* PD720122F1-GN2 : 109-pin plastic FBGA (11 x 11)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less Exposure limit: 3 daysNote (after that, prebake at 125C for 10 hours) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Symbol IR35-103-3
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Data Sheet S16685EJ2V0DS
79
PD720122
[MEMO]
80
Data Sheet S16685EJ2V0DS
PD720122
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S16685EJ2V0DS
81
PD720122
EEPROM is a trademark of NEC Electronics Corporation. USB logo is a trademark of USB Implementers Forum, Inc.
* The information in this document is current as of June, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

▲Up To Search▲

Price & Availability of UPD720122

	To Download UPD720122 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .